1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to an inside nitride spacer for deep trench device DRAM cells.
2. Discussion of Prior Art
The development of deep trench dynamic random access memory (DRAM) cells has led to fast chips having smaller critical dimensions and greater storage capacity. Among various memory types, deep trench DRAM cells in particular need space, and therefore high-density deep trench DRAM cells have been difficult to achieve. One problem is that deep trench DRAM cells can be prone to wordline (WL) to bitline (BL) shorts.
A wordline can be protected by a nitride spacer and cap as in prior planar array device DRAM cells. In the trench-sidewall vertical device DRAM cell the WL runs directly over the gate poly of the vertical device, which is buried in the top part of the trench. Since the WL is typically about 30% narrower then the top width of the trench, the WL does not cap the trench completely. Even after the spacer is put in place, and assuming a perfect WL to deep trench alignment, the top of the vertical gate poly is unprotected and can connect to the contact bitline.
Planar array device technologies include nitride spacers to protect the sidewall of the gate conductor line and prevent shorts. The top deep trench width is typically larger than the gate conductor line width. Therefore, only a deep trench top spacer, which has a good overlap to the gate conductor spacer, can provide continuous protection against a bitline contact.
Gate conductor shorts caused by stringers are a particular problem in deep trench cells within vertical devices. The stringers are poly Si stringers along the isolation trench boundaries within the trench, along the short axis of the trench. The shorts are typically created during the isolation trench process and can be fixed after the active area (AA) structuring process. Specific failures result from poly stringers being left after gate etch, vias, or contacts that did not open.
Therefore, a need exists for an inside nitride spacer for deep trench device DRAM cells for isolating bitline contacts from wordlines.